124 Chapter
6
library IEEE;
use IEEE.ELECTRICAL_SYSTEMS.all, IEEE.FUNDAMENTAL_CONSTANTS.all;
entity RESISTOR is
generic (VALUE_R : REAL := 1.0; -- resistance [Ohm]
TEMP : REAL := 300.0); -- temperature [K]
port (terminal P1, P2 : ELECTRICAL);
begin
assert VALUE_R > 0.0 and TEMP > 0.0
report "ERROR: Parameters are not correct." severity ERROR;
end entity RESISTOR;
architecture NOISY of RESISTOR is
quantity V
across I, INOISE through P1 to P2; -- parallel br.
quantity SI : REAL noise 4.0*PHYS_K*TEMP/VALUE_R;
begin
V == VALUE_R * I;
INOISE == SI;
end architecture NOISY;
6.7
Summary
In this chapter we gave a short introduction to VHDL-AMS. The basic
language constructs and ideas of VHDL-AMS were explained. More
information can be found in the IEEE Std 1076.1. We focused on the analog
extension of VHDL-AMS compared to the pure digital oriented VHDL.
Some new features in VHDL-AMS consist of:
Language constructs to describe conservative network semantics
(terminals, natures, branch quantity declarations)
Language constructs to describe nonconservative signal flow
semantics (quantity ports)
Simultaneous statements to describe analog constitutive relations
Special support to model analog behavior ('DOT, 'INTEG,
'DELAYED, 'LTF, 'ZOH, 'ZTF, and other attributes)
Support to model mixed-signal interaction between analog and
digital parts ('ABOVE, 'RAMP, 'SLEW attributes, and break
statement)
Definition of the mixed-signal simulation cycle
Usage of the DOMAIN signal to distinguish between different kinds
of analysis (QUIESCENT_DOMAIN, TIME_DOMAIN, and
FREQUENCY_DOMAIN including small signal AC and noise
analysis)
In this chapter we did not consider facilities to model multi-domain
systems consisting of electrical and nonelectrical parts. Some other language
extensions were also not considered (for example the full break statement).