SELECTED RF BLOCKS IN VHDL-AMS
135
quantity V_ROUT across I_ROUT through P to N_INT;
quantity V_SRC
across I_SRC
through N_INT to M;
begin
if NOW > INITDELAY and EFFFREQ < STOPFREQ use
EFFFREQ == STARTFREQ + SWEEPRATE*(NOW-INITDELAY);
elsif EFFFREQ >= STOPFREQ use
EFFFREQ == STOPFREQ;
else
EFFFREQ == STARTFREQ;
end use;
if DOMAIN = QUIESCENT_DOMAIN USE
PHI == 0.0;
else
PHI'DOT == MATH_2_PI*EFFFREQ;
end use;
-- signal source
V_SRC == 2.0 * AMP * SIN(PHI);
-- output port resistance
V_ROUT == ROUT * I_ROUT;
end architecture BHV;
The model implementation is included on the CD-ROM that is provided
with this book.
7.2.4
Pseudorandom binary source
Functional description
This model provides a pseudorandom sequence at its binary output. It is
constructed as a maximum-length feedback shift register with variable
register length.
bit_out
D
D
D
...
...
k
x
1
k
x
2
k
x
1
k n
x
k n
x
1
h
n
h
2
h
1
n
h
Figure 7-7. Block diagram of a pseudorandom binary source (PRBS)
Summary :
k x 1 k x 2 k x 1 k n x k n x 1 h n h 2 h 1 n h Figure 7-7.
Tags :
efffreq,use,binary,end,rout,stopfreq,pseudorandom,source,nint,register,through,output,quantity