156 Chapter
7
quantity V_RIN
across I_RIN
through P_CTRL to GND;
quantity V_ROUT across I_ROUT through P_OUT to N_INT;
quantity V_SRC
across I_SRC
through N_INT to GND;
begin
process (STATE,V_RIN'ABOVE(-FREQ_0/K_FREQ))
VARIABLE F: REAL;
begin
if STATE='1' THEN
FACTOR<=1.0;
else
FACTOR<=-1.0;
end if;
F := FREQ_0 + K_FREQ*V_RIN;
if F>0.0 then
STATE <= not STATE after 0.5/F*SEC;
end if;
end process;
break on STATE;
-- input impedance
V_RIN == RIN * I_RIN;
-- tunable oscillator
V_SRC == 2.0*(DC+FACTOR*AMPL);
-- output impedance
V_ROUT == ROUT * I_ROUT;
end architecture digital;
The complete model is included on the CD-ROM that is provided with
this book.
Simulation example
A piecewise linear signal was applied as the control voltage, which
changes at 10.2 ms from 0 to 15 mV, and at 12.2 ms to 5 mV. The VCO
model was instantiated with the following parameters:
LO: entity VCO(DIGITAL)
generic map ( AMPL_DBM => -30.0,
FREQ_0 => 1.0e03,
K_FREQ => 1.0e05)
port map (P_CTRL => N_CTRL,
P_OUT => N_CLK,
VDD => N_VDD,
GND => ELECTRICAL_REF);
The complete test bench is included on the CD-ROM that is provided
with this book.