COMPLEX EXAMPLE: WLAN RECEIVER
Section 7.5. Additional ideal splitter blocks are introduced in order to split
the signal without any loss due to impedance mismatch. For the intended
application of the PLL as a frequency synthesizer, the output outclk is
relevant, whereas other applications such as FM demodulators require the
output out after the loop filter.
Figure 9-4. Block diagram of the modeled PLL
The center frequency of the PLL can be parameterized with the free
running frequency of the VCO and is set to 2.6 GHz. Also, the initial phase
offset and the signal power of the local oscillator can be adjusted in the VCO
of the PLL.
Phase noise and orthogonality error are not included here. An oscillator
model including phase noise is used in Chapter 10 for RF analyses of the
WLAN receiver. The VHDL-AMS model of the PLL in Figure 9-4 can be
found on the CD-ROM.
The PLL is fed by another VCO that has the same center frequency of
2.6 GHz. At the output of the PLL a phase shifter to splits the local oscillator
clock into in-phase (I) and quadrature (Q) components. A simple ideal phase
shifter model has been implemented that works at the specified LO
Other elements of the receiver include the highpass filter between the
stages. Here we use simple capacitors that, together with the input
impedance of the following stage, form a first-order highpass filter. A corner
frequency of 1 GHz has been chosen to suppress DC offsets effectively.
The splitter block in the receiver is again ideal and identical to the one
used for the PLL. Ideal in this sense means that the input signal is identically
transferred to both outputs without any loss. To overcome the effect that the
power is doubled in this case, which is unrealistic, further model refinements