214 Chapter
9
9.5
Example Verification
Verification of the WLAN receiver example is done using hierarchical
composition of the modeled subblocks in terms of a bottom-up verification.
Usually the subblock models have been individually calibrated and
optimized using circuit models. After combining the optimized subblock
models the overall system behavior is simulated. It is then possible to
analyze whether the overall design goals and performance measures are met,
bearing in mind the limited accuracy of the behavioral models.
For system level verification of the receiver design example we use the
behavioral models that were described in Section 9.3. A system level test-
bench for the receiver should include:
Complete system level model for the design under test (DUT)
Signal source to stimulate the DUT
Signal processing block to adapt the source signal to the needs of the
DUT
Analysis blocks
Once a test-bench with these elements is established individual blocks
can be replaced by more accurate ones or by circuit level implementations of
the same block. Thereby the influence of this block on system level
performance measures can be explored without needing to simulate the
whole design at circuit level.
The treated receiver design example is completed with a binary source, a
digital-to-analog converter (DAC) and the test transmitter to form the system
level test-bench. Strictly speaking this is a pure RF test-bench since all
baseband signal processing is neglected. Figure 9-9 shows the test-bench
configuration to verify the receiver design example.
Figure 9-9. Testbench for system level verification
For the sake of simplicity only the in-phase channel (I) of the
transmission system is considered in this example. A pseudorandom binary
Summary :
A system level test- bench for the receiver should include: Complete system level model for the design under test (DUT) Signal source to stimulate the DUT Signal processing block to adapt the source signal to the needs of the DUT Analysis blocks Once a test-bench with these elements is established individual blocks can be replaced by more accurate ones or by circuit level implementations of the same block.
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system,leel,example,design,testbench,erification,models,receier,signal,source,test,dut,block