MODELING OF ANALOG BLOCKS IN VERILOG-A
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The basis for behavioral and structural descriptions are modules. The
module lp_filter (see listing below) shows the basic structure of a Verilog-A
module. Port and signal declarations are used to describe the interface of the
module. In the parameter declaration electrical or other physical values are
defined. Other declaration types like real or integer are also possible. The
underlying description of the module behavior is done with a structural or a
behavioral part. All description types, system types, and disciplines can be
combined in a single Verilog-A model.
module lp_filter (sig1, sig2, gnd);
inout sig1, sig2, gnd;
electrical sig1, sig2, gnd;
parameter real R = 1k;
parameter real C = 1u;
// structural description, see lp_filter_str
// behavioral description, see lp_filter_beh
endmodule
In a structural description several modules can be instantiated and
connected. In this case the design becomes hierarchical and facilitates the
top-down design process. The module lp_filter_str shows the structural
description of a lowpass filter, where the modules of the resistor and the
capacitor are instantiated.
module lp_filter_str (sig1, sig2, gnd);
inout sig1, sig2, gnd;
electrical sig1, sig2, gnd;
res res_inst (.r_in(sig1), .r_out(sig2));
cap cap_inst (.c_in(sig2), .c_out(gnd));
endmodule
A behavioral description contains the mathematical relationships between
input signals, output signals and parameters. For that purpose Verilog-A
contains a rich set of analog operators and functions. The module
lp_filter_beh
shows the behavioral description of the lowpass filter using the
ddt
time derivative operator.
module lp_filter_beh (sig1, sig2, gnd);
inout sig1, sig2, gnd;
electrical sig1, sig2, gnd;
parameter real R = 1k;
parameter real C = 1u
analog begin
I(sig1, sig2) <+ V(sig1, sig2)/R;
I(sig2, gnd) <+ ddt(V(sig2, gnd)*C);
end
endmodule