Since the ground pins must return current to the power supply and the power pins must
supply it to the drivers, low inductance is typically required for both power and ground paths
to minimize inductive noise whether the return currents are flowing in the power or ground
pins. Subsequently, it is generally optimal to maximize the total number of power and ground
pins to decrease the total inductive path. In the equations above, it will effectively decrease
L
gg
. Furthermore, it is usually optimal to place power and ground pins adjacent to each other
because the currents flows in opposite directions. Subsequently, the total inductance of the
ground and power pins is reduced by the mutual inductance.
5.2.5. EMI
Another detrimental effect of a bad connector design is increased EMI radiation, covered in
detail in
Chapter 10
. Notice the large current loops in
Figure 5.4
. As explained in detail in
Chapter 10
, the area of the loop is proportional to the emission radiated. Connectors will also
exacerbate simultaneous switching noise by increasing the inductance in the ground return
path and signal paths. Simultaneous switching noise and ground return path analysis are
covered in detail in
Chapter 6
.
5.2.6. Connector Design Guidelines
Based on the analysis above, several general connector design guidelines can be made.
The most obvious is to minimize the physical length of the connector pins to reduce the total
series inductance. It is also desirable to maximize the power and ground to signal pin ratio.
This will minimize the effect of the power and ground pin inductances. The placement of the
power and ground pins should minimize the current loops and decrease connector-related
radiated emissions. Each signal pin should be placed in close proximity to a power and a
ground pin.
It should be noted that in cases where a large fraction of signals routed through a connector
are differential, several of the design guidelines listed here will need modification. For
instance, for connectors or packages that carry mostly differential signals, the number of
power and ground pins required will probably be far less than those for a similar single-
ended system. Furthermore, differential signals may sometimes be grouped together in large
banks without power or ground pins separating them.
Several conclusions can be drawn from the discussion above.
1. Since coupling of signal pins to current return pins decreases the total inductance, it is
optimal that each signal pin be tightly coupled to a current return pin (by placing them
in close proximity to each other). The bus type and configuration will determine
whether each signal should be coupled to both a power and a ground pin, just a
ground pin, or just a power pin. In
Chapter 6
we discuss how to determine where the
return current is flowing. If the return current is flowing in the ground planes, the
signal pins should be coupled to the ground pins. If the return current is flowing
through the power planes, the signal pins should be coupled to the power pins. If the
return current is flowing through both planes, each pin should, if possible, be coupled
to both a power and a ground pin.
2. The power and ground pins should be placed adjacent to each other to minimize the
inductance seen in the power and ground paths.
3. It is generally optimal to design a connector so that the ratio of power pins to signal
pins and the ratio of ground pins to signal pins are greater or equal to 1. This will
minimize the total return path inductance. This may not be as dominant a concern in
differential systems.
4. It is generally optimal to use the shortest connector possible to minimize inductive
effects and impedance discontinuities.