Figure 5.11: Equivalent circuit developed for
Example 5.2
.
sections of each section are shown in
Figure 5.10b
. Once the mutual parasitics are known,
the coupling factor, K, is calculated with
equation (3.12)
. Coupling between bond wires
should not be ignored because it can have significant impact. As a general rule of thumb, the
inductance of a typical bond wire will be approximately 1 nH for each 50 mils of length. The
capacitive parasitics of the bond wires have been ignored at this stage because they are
extremely small and can usually be ignored. Although the power and ground bond wires are
not included in this model, they can be dealt with in the same manner as power and ground
pins in a connector array, as described earlier in this chapter. This is explored in more detail
in
Chapter 6
. The equivalent circuit is depicted on the left-hand side of
Figure 5.11
, where
C
pad chip
is the I/O capacitance of the die, L
A
and L
B
are the bond wire inductance, and C
pad
pack
represents the bonding pad on the package (where the bond wire attaches to the
package).
Routing of the signals on the package. It is usually adequate to consider either three or five
coupled signals on a package because coupling effects tend to reduce very quickly with
distance. It should be noted, however, that densely routed traces tend to couple to multiple
traces as they wind their way from driver to receiver. Subsequently, it is important to observe
the package routing and determine which signals must be considered to achieve the
nearest-neighbor coupling. In this particular example, trace 2 would be considered the target
net, and lines 1 and 3 will be excited to account for crosstalk effects. The traces are
separated into four sections represented by cross section A through D in
Figure 5.10c
. In
section A, all three lines are coupled; in section B, only lines 2 and 3 are coupled; in section
C, lines 1 and 2 are coupled; and finally, in section D, only line 1 continues because it is the
longest. The package routing should entail all of the applicable effects outlined in Chapters 2
through 4, including losses. Losses are often ignored in package designs, which is a mistake
because small dimensions tend to make them significantly more lossy than typical PCB
traces. The models of the package routes are shown in the middle of
Figure 5.11
.
Attachment of the package to the PCB. This example is a BGA attachment. Subsequently,
the major contributor to the performance will simply be the pad capacitance on the package
and on the PCB. The via parasitics and the ball inductance will usually be small. The via
parasitics can be estimated with
equations (5.1)
and
(5.2)
. The ball inductance will usually
be on the order of 0.5 nH. The only way to model the effect of the ball inductance rigorously
is to use a three-dimensional simulator or to measure it. This section is shown on the right-
hand side of
Figure 5.11
. C
via
and L
via
are the parasitics of the via that connects the package
trace to the ball pad, C
ball pad
and L
ball
are the parasitics of the solder ball and pad, and C
ball pad
PCB
is the capacitance of the attachment pad on the PCB.
Example 5.3: Modeling a Pin-Grid-Array Attachment.