6.2. LOCAL POWER DELIVERY NETWORKS
Power delivery will initially be discussed only as it pertains to the performance of the I/O
buffers and the interconnects on the bus. The reader should note that although the analysis
of local power delivery networks share much in common with system-level power delivery,
the focus is different. The focus is supplying the required high-frequency current to the I/O
Consider the LC ladder to the left of the GTL output buffer depicted in
. This is a
very simplified network intended to represent the power supply as seen through the eyes of
the output buffer. The ideal voltage supply represents the voltage at the system voltage
regulator module (VRM), which provides a stable dc voltage to the system. The first 10-nH
inductor crudely represents the inductive path between the VRM and the first bulk
decoupling capacitor, whose value is 2 µF. The 5-nH inductor represents the path
inductance between the bulk decoupling capacitor and the I/O cell on the die. As mentioned
above, the capacitor C represents the local decoupling on the die at the I/O cell. As
mentioned earlier, this is only a very crude representation of a power delivery system;
however, it is adequate to achieve first-order approximations and is excellent for instructional
purposes. A full model would require extraction from a three-dimensional simulator (or
measurements) and would be implemented in a simulator with a mesh of inductors that
resembles a bedspring. Alternatively, full-wave simulators that use the finite-difference time
domain (FDTD)-based algorithms can be used to optimize the local power delivery system.
The FDTD simulator approach will yield more accurate responses of the board and package
interactions; however, it is usually very difficult or impossible to model the active circuitry
correctly in such simulators. To approximate the first-order effects, however, it is adequate to
represent the power delivery system in the simplified manner discussed here and to ensure
that the decoupling capacitance is adequate so that the local power delivery system will not
affect the signal integrity.
The problem is that when the output buffer switches, it quickly tries to draw current from the
VRM. The series inductance to the VRM will limit the current that can be supplied during the
switching time. If the inductance is large enough, it will essentially isolate the output buffer
from the power supply when current is drawn at a fast rate. If the inductance is high enough,
it essentially looks like an open circuit during fast transitions and will block the flow of current.
Subsequently, the power seen at the I/O cell will droop because the local power delivery
system cannot supply the required current. This effect has many names, including power
droop, ground bounce, and rail collapse. Whatever it may be called, it can devastate the
signal integrity if not accounted for properly.
Ideally, the elimination, or the significant reduction of the series inductance, will solve the
problem of rail collapse. However, reality eliminates the ideal solution because it is
impossible to place a VRM in close proximity to every I/O cell. The next best thing is to place
decoupling capacitors as close as possible to the component. The decoupling capacitors will
be charged up by the VRM and will act like local batteries or mini power supplies to the I/O
cell. If the decoupling capacitance is large enough and the series inductance to the
decoupling capacitors is small, they will supply the necessary current during the transition
and preserve the signal integrity.
depicts the signal integrity as a function of local
I/O capacitance. The capacitance C represents the local capacitance at the I/O cell as
. Notice that the signal integrity gets progressively better as
the local capacitance is increased.
Another effect of power droop is a timing push-out in the form of a ledge, as shown in
. This effect is quite common, especially in CMOS