Figure 6.17: Simultaneous switching noise mechanisms.
SSN can be a very elusive noise to characterize. There are not many methods for quick
approximations to get an easy assessment of SSN. Only careful examination of your
package and power delivery system and detailed simulations can lead to a reasonable
assessment of the magnitude of SSN. Even when attempts are made to characterize the
noise accurately, it is almost impossible to determine an exact answer because the variables
are so numerous and the geometries that must be assessed are three-dimensional in nature
and depend heavily on the individual chip package (or connector) and the pin-out. Because
of the difficulty of this problem, it is recommended that SSN be evaluated using both
simulation and measurements. Subsequently, only general rules can be used to control this
is a generic model that can be used to evaluate SSN in a CMOS bus. The
, are the inherent on-die capacitance for each I/O cell. L
inductance seen on the chip between the CMOS gate and the power bus. L
the inductance of the power distribution on the die and package. L
inductance of the ground distribution on the die and on the package.
represent the inductance of the power and ground pins on the package. L
the inductive path between the pin and the nearest decoupling capacitor. L
series inductance of the decoupling capacitors, and
represents the board-level
decoupling capacitors. Finally, L
represents the series inductance of the package seen at
the I/O outputs. It should be noted that all mutual inductance values should be included in
this model. Furthermore, the number of gates simulated should be equal to the number of
gates that share the same power and ground pins.
L pwr bus represents the inductance of the power distribution on the die and package. and L gnd pin represent the inductance of the power and ground pins on the package. L cap represents the series inductance of the decoupling capacitors, and represents the board-level decoupling capacitors.