Subsequently, the most useful form of the setup margin equation is
A common-clock design will function correctly only if the setup margin is greater than or
equal to zero. The easiest way to compensate for a setup timing violation is to lengthen the
clock trace for the receiver, shorten the clock trace to the driver, and/or shorten the data
trace between the driver and receiver flip-flop.
To latch a signal into the receiver successfully, it is necessary that the data signal remain
valid at the input pin long enough to ensure that the data can be clocked in without error.
This minimum time is called the hold time. In a common-clock bus design, all the circuit and
transmission line delays must be accounted for to ensure proper timing relationships to
satisfy the hold-time requirements at the receiver. However, even though the second edge in
a common clock transaction latches in the data at the receiver flip-flop, it also initiates the
next transfer of information by latching data to the output of the driver flip-flop. Subsequently,
the hold timing equations must also ensure that the valid data are latched into the receiver
before the next data bit arrives. This requires that the delay of the clock path plus the
component hold time be less than the delay of the data path. It is basically a race to see
which signal can arrive at the receiver first, the new data signal or the clock signal.
To derive the hold-time equation, refer to the dashed arrows in
. The delay of the
receiver clock and the delay of the next data transaction must be compared to ensure that
the data are properly latched into the receiver before the next data signal arrives at the
receiver pin. The clock and data delays are calculated as
Notice that neither the cycle time nor the clock jitter are included in
. This is
because the hold time does not depend on the cycle time, and clock jitter is defined as cycle-
to-cycle period variations. Since the clock cycle time is not needed to calculate hold margin,
jitter is not included.
The subsequent hold-time margin is calculated as
If the substitutions of
are made, the useful equation for design is
RULES OF THUMB: Common-Clock Bus Design
Common-clock techniques are generally adequate for medium-speed buses with
frequencies below 200 to 300 MHz. Above this frequency, other signaling
techniques, such as source synchronous (introduced in the next section), should be
The component delays and the delays of the PCB traces place a hard theoretical limit
on the maximum speed a common-clock bus can operate. Subsequently, a
maximum limit is placed on the lengths of the PCB traces.