9.1. TIMINGS
The only thing that really matters in a digital design is timings. Some engineers argue that
cost is the primary factor; however, the cost assumption is built into most designs. If the
design does not meet the specific cost model, it will not be profitable. If the timing equations
presented in
Chapter 8
are not solved with a positive margin, the system simply will not work.
Every concept in this book somehow relates to timings. Even though several chapters in this
book have concentrated on such things as voltage ringback or signal integrity problems, they
still relate to timings because signal integrity problems matter only when they affect timings
(or destroy circuitry, which makes the timing equations unsolvable). This chapter will help the
reader relate all the high-speed issues discussed in this book back to the equations
presented in
Chapter 8
.
The first step in designing a digital system is to roughly define the initial system timings. To
do so, it is necessary to obtain first-order estimates from the silicon designers on the values
of the maximum and minimum output skew, T
co
, and setup and hold times for each
component in the system. If the silicon components already exist, this information will usually
be contained in the data sheet for the component. A spreadsheet should be used to
implement the digital timing equations derived in
Chapter 8
or the appropriate equations that
are required for the particular design. The timing equations are solved assuming a certain
amount of margin (presumably zero or a small amount of positive margin). Whatever is left
over is allocated to the interconnect design. If there is insufficient margin left over to design
the interconnects, either the silicon numbers need to be retargeted and redesigned, or the
system speed should be decreased.
The maximum and minimum interconnect delays should initially be approximated for a
common-clock design to estimate preliminary maximum and minimum length limits for the
PCB traces and to ensure that they are realistic. If the maximum trace length, for example, is
0.15 in., it is a good bet that the board will not be routable. To do this, simply set the setup
and hold margins to zero (using the equations in
Chapter 8
), solve for the trace delays, and
translate the delays to inches using an average propagation speed in FR4 of 150 ps/in. for a
microstrip or 170 ps/in. for a stripline. Of course, if the design is implemented on a substrate
other than FR4, simply determine the correct propagation delay using
equation (2.3)
or
(2.4)
using an average value of the effective dielectric constant. In a source synchronous design,
the setup and hold margins should be set to zero and the PCB skew times should be
estimated. Again, the skews should be checked at this point to ensure that the design is
achievable.
It should be noted that every single value in the spreadsheet is likely to change (unless the
silicon components are off-the-shelf parts). The initial timings simply provide a starting point
and define the initial design targets for the interconnect design. They also provide an initial
analysis to determine whether or not the bus speed chosen is realistic. Typically, as the
design progresses, the silicon and interconnect numbers will change based on laboratory
testing and/or more detailed simulations.
9.1.1. Worst-Case Timing Spreadsheet
A spreadsheet is not always necessary for a design. If all the components are off the shelf, it
may not be necessary to design with a spreadsheet because the worst-case component
timings are fixed. However, if the components, such as a processor, chipset, or a memory
component, is being developed simultaneously with the system, the spreadsheet is an
extremely valuable tool. It allows the component design teams (i.e., the silicon designers)
and the system design teams to coordinate with each other to produce a working system.
The spreadsheet is updated periodically and is used to track progress, set design targets,
and perform timing trade-offs.