9.2. TIMING METRICS, SIGNAL QUALITY METRICS, AND TEST
After creating the initial spreadsheet with the target numbers, specific timing and signal
quality metrics must be defined. These metrics allow the calculation of timing numbers for
inclusion into the spreadsheet and provide a means of determining whether signal quality is
9.2.1. Voltage Reference Uncertainty
The receiver buffers in a digital system are designed to switch at the threshold voltage.
However, due to several variables, such as process variations and system noise, the
threshold voltage may change relative to the signal. This variation in the threshold voltage is
known as the V
uncertainty. This uncertainty is a measure of the relative changes between
the threshold voltage and the signal.
depicts the variation in the threshold voltage
(known as the threshold region).
Figure 9.4: Variation in the threshold voltage.
Signal quality, flight time, and timing skews are measured in relation to the threshold voltage
and are subsequently highly dependent on the size of the threshold region. The threshold
region includes the effects on both the reference voltage and the signal. The major effects
that typically contribute to the V
Power supply effects (i.e., switching noise, ground bounce, and rail collapse)
Core noise from the silicon circuitry
Receiver transistor mismatches
Return path discontinuities
Coupling to the reference voltage circuitry
The threshold region typically extends 100 to 200 mV above and below the threshold voltage.
The upper and lower levels will be referred to as V
, respectively. The V
is important to quantify accurately early in the design cycle because it accounts for
numerous effects that are very difficult or impossible to model explicitly in the simulation
environment. Often, they are determined through the use of test boards and test chips.
9.2.2. Simulation Reference Loads
the concept of a timing spreadsheet is introduced. It is important that all the
numbers entered into the spreadsheet (or timing equations) are calculated in such a manner
that they add up correctly and truly represent the timings of the entire system. This is done
with the use of a standard simulation test load (referred to as either the standard or the
reference load). The reference load is used by the silicon designers to calculate T
setup/hold times, and output skews. The system designers use it to calculated flight times
and interconnect skews. The reference load is simply an artificial interface between the