silicon designer world and the system designer world that allows the timings to add up
correctly. This is important because the silicon is usually designed in isolation of the system.
If the silicon timing numbers are generated by simulating into a load that is significantly
different from the load the output buffer will see when driving the system, the sum of the
silicon-level timings and the board-level timings will not represent the actual system timings.
shows how simulating the T
timings into a load that is different
from the system can artificially exaggerate or understate the timings of the system. The top
portion of the figure depicts the T
time of an output buffer driven into a load that does not
resemble the system input. The bottom portion represents the total delay of a signal in the
system (shown as the output buffer driving a transmission
Figure 9.5: Illustration of timing problems that result if a standard reference load is not
used to insert timings into the spreadsheet.
line). The actual delay the signal experiences between the driver and receiver in the system
. If the silicon T
numbers are calculated with a load that does not look
electrically similar to the system, then the total delay will be T
, which will not
To prevent this artificial inflation or deflation of calculated system margins, the component
timings should be simulated with a standard reference load. The same load is used in the
calculation of system-level flight times and skews. This creates a common reference point to
which all the timings are calculated. This prevents the spreadsheets from incorrectly adding
board- and silicon-level timings. If this methodology is not performed correctly, the predicted
timing margins will not reflect reality. Since the timing spreadsheets are the base of the
entire design, such a mistake could lead to a nonfunctional design. In the sections on flight
time and flight-time skew we explain in detail how to use this load.
Choosing a Reference Load.
Ideally, the reference load should be very similar to the input of the system. It is not
necessary, however, that the reference load be electrically identical to the input to the
system, just similar enough that the buffer characteristics do not change. Since the standard
load acts as a transition between silicon and board timings, small errors will be canceled out.
This is demonstrated with
the reference load is different from the
input to the system. However, since the load is used as a reference point, the total delay is
calculated correctly when the timings are summed in the spreadsheet. The top waveform
depicts the T