4. Simple linear buffers are used that are easy to sweep.
With these assumptions in place, the designer can quickly run numerous simulations to pick
the topologies, the initial line lengths, minimum trace spacing, buffer impedances,
termination values and PCB impedance values. Future simulations will incorporate the more
computationally intensive effects. After the completion of the phase 1 solution space, the
initial buffer parameters, such as impedance and edge rates, should be given to the silicon
designers. This will allow them to design the initial buffers, which are needed for the phase 2
Phase 1 ISI.
Intersymbol interference (ISI) also needs to be accounted for in the parameter sweeps. ISI is
simply pattern-dependent noise or timing variations that occur when the noise on the bus
has not settled prior to the next transition (see
). To estimate ISI in a system, it is
necessary to simulate long pseudorandom pulse trains. This technique, however, is long,
cumbersome, and very difficult to do during a parameter sweep. The following technique will
allow the designer to gain a first-order approximation of the ISI impact in the phase 1
solution space. The full effect of the ISI will be evaluated later.
To capture most of the timing impacts due to intersymbol interference, the parameter
sweeps (for all eight worst-case corners) should be performed at the fastest bus frequency,
and then at 2× and 3× multiples of the fastest bus period. For example, if the fastest
frequency the bus will operate at produces a single bit pulse duration of 1.25 ns, the data
pattern should be repeated with pulse durations of 2.5 and 3.75 ns. This will represent the
following data patterns transitioning at the highest bus rate.
The timings should be taken at each transition for at least five periods so that the signal can
reach steady state. The worst-case results of these should be used to produce the phase 1
solution space. This will produce a first-order approximation of the pattern-dependent impact
on the bus design. This analysis can be completed in a fraction of the time that it takes to
perform a similar analysis using long pseudorandom patterns. Additionally, since the worst
signal integrity will often occur at a frequency other than the maximum bus speed, this
technique helps ensure that signal integrity violations are not masked by the switching rate
Monte Carlo Double Check.
After the phase 1 solution space is determined, it is a good idea to perform a final check.
Monte Carlo analysis can used as a double check on the phase 1 solution space to ensure
passing margin under all conditions. Although the IMC analysis is designed to ensure that
the parameter sweeps will yield the worst-case conditions, it is possible that the worst-case
combination of variables was not achieved. During the Monte Carlo analysis, the results of
the metric (i.e., the flight time or the skew) should be observed, as all the individual
components of the design are bounded by the constraints of the phase 1 solution space and
varied randomly. The maximum and minimum values should be compared to the
specifications. If there are any violations, the specific conditions that caused the failure
should be observed so that the mechanism can be established. Therefore, it is necessary to
keep track of the Monte Carlo output and the random input variables so that a specific output
can be correlated to all the input variables. It is sometimes useful to plot the output of the
Monte Carlo analysis against specific variables as was done in the initial Monte Carlo
analysis. This often provides significant insight into the cause of the failure.