Return current for a GTL buffer driving a power referenced microstrip line: (a)
pull-down; (b) pull-up.
Signal integrity as a function of local decoupling capacitance: (a) power-
plane-referenced microstrip; (b) ground-plane-referenced microstrip. (Circuits simulated
are shown in Figures 6.8 and 6.9.)
(a) Unbalanced versus (b) balanced transmission line models.
Telltale sign of a power delivery problem.
Estimating the area where the current will flow from the component to the
Equivalent circuit of three GTL drivers and a component-level power
delivery system. C, on-die I/O cell capacitance; C
, first-level decoupling capacitor; L
package and socket equivalent inductance; L
, PCB plane inductance from package
power pin to decoupling capacitor; L
, inductance to the VRM; L
, lead inductance of the
Impedance versus frequency for a discrete bypass capacitor.
Frequency response of a simple power delivery system.
Simultaneous switching noise mechanisms.
Model used to evaluate component level SSN/SSO for a CMOS-driven bus.
Generic buffer implementation.
Basic CMOS output buffer.
General method of describing buffers elsewhere in this book.
NMOS and PMOS I-V curves.
CMOS output buffer driving a load.
Operation of the CMOS output buffer when the input voltage is (a) high and
Ideal I-V curve with a fixed impedance.
Different regions of the I-V curve exhibit different impedance values.
Variations in the buffer impedance at a constant V
due to fabrication
variations and temperature.
Buffer in series with a resistor.
Effect of increasing the series resistor.
(a) Most simplistic linear model of a CMOS buffer; (b) another simplistic