Figure 6.9:
Return current for a GTL buffer driving a power referenced microstrip line: (a)
pull-down; (b) pull-up.
Figure 6.10:
Signal integrity as a function of local decoupling capacitance: (a) power-
plane-referenced microstrip; (b) ground-plane-referenced microstrip. (Circuits simulated
are shown in Figures 6.8 and 6.9.)
Figure 6.11:
(a) Unbalanced versus (b) balanced transmission line models.
Figure 6.12:
Telltale sign of a power delivery problem.
Figure 6.13:
Estimating the area where the current will flow from the component to the
decoupling capacitor.
Figure 6.14:
Equivalent circuit of three GTL drivers and a component-level power
delivery system. C, on-die I/O cell capacitance; C
1
, first-level decoupling capacitor; L
1
,
package and socket equivalent inductance; L
2
, PCB plane inductance from package
power pin to decoupling capacitor; L
3
, inductance to the VRM; L
c
, lead inductance of the
capacitor.
Figure 6.15:
Impedance versus frequency for a discrete bypass capacitor.
Figure 6.16:
Frequency response of a simple power delivery system.
Figure 6.17:
Simultaneous switching noise mechanisms.
Figure 6.18:
Model used to evaluate component level SSN/SSO for a CMOS-driven bus.
Chapter 7:
Buffer Modeling
Figure 7.1:
Generic buffer implementation.
Figure 7.2:
Basic CMOS output buffer.
Figure 7.3:
General method of describing buffers elsewhere in this book.
Figure 7.4:
NMOS and PMOS I-V curves.
Figure 7.5:
CMOS output buffer driving a load.
Figure 7.6:
Operation of the CMOS output buffer when the input voltage is (a) high and
(b) low.
Figure 7.7:
Ideal I-V curve with a fixed impedance.
Figure 7.8:
Different regions of the I-V curve exhibit different impedance values.
Figure 7.9:
Variations in the buffer impedance at a constant V
gs
due to fabrication
variations and temperature.
Figure 7.10:
Buffer in series with a resistor.
Figure 7.11:
Effect of increasing the series resistor.
Figure 7.12:
(a) Most simplistic linear model of a CMOS buffer; (b) another simplistic
linear approach.