Obviously a digital receiver must also know where a time slot begins and ends. If we
can synchronize a frame, time-slot synchronization can be assured. Frame synchronization
assumes that bit synchronization has been achieved. We know where a frame begins (and
ends) by some kind of marking device. With DS1 it is the framing bit. In some frames
it appears as a 1 and in others it appears as a 0. If the 12-frame super-frame is adopted,
it has 12 framing bits, one in each of the 12 frames. This provides the 000111 framing
pattern (Ref. 3). In the case of the 24-frame extended superframe, the repeating pattern
is 001011, and the framing bit occurs only once in four frames.
E1, as we remember from Section 6.2, has a separate framing and synchronization
channel, namely, channel 0. In this case the receiver looks in channel 0 for the framing
sequence in bits 2 through 8 (bit 1 is reserved) of every other frame. The framing sequence
is 0011011. Once the framing sequence is acquired, the receiver knows exactly where
frame boundaries are. It is also time-slot aligned.
All digital switches have a master clock. Outgoing bit streams from a switch are slaved
to the switch's master clock. Incoming bit streams to a switch derive timing from bit tran-
sitions of that incoming bit stream. It is mandatory that each and every switch in a digital
network generate outgoing bit streams whose bit rate is extremely close to the nominal
bit rate. To achieve this, network synchronization is necessary. Network synchronization
can be accomplished by synchronizing all switch (node) master clocks so that transmis-
sions from these nodes have the same average line bit rate. Buffer storage devices are
judiciously placed at various transmission interfaces to absorb differences between the
actual line bit rate and the average rate. Without this network-side synchronization, slips
will occur. Slips are a major impairment in digital networks. Slip performance require-
ments are discussed in Section 18.104.22.168. A properly synchronized network will not have
slips (assuming negligible phase wander and jitter). In the next paragraph we explain the
fundamental cause of slips.
As mentioned, timing of an outgoing bit stream is governed by the switch clock.
Suppose a switch is receiving a bit stream from a distant source and expects this bit
stream to have a transmission rate of
F (0) in Mbps. Of course, this switch has a buffer
of finite storage capacity into which it is streaming these incoming bits. Let's further
suppose that this incoming bit stream is arriving at a rate slightly greater than
F (0), yet
the switch is draining the buffer at exactly
F (0). Obviously, at some time, sooner or later,
that buffer must overflow. That overflow is a slip. Now consider the contrary condition:
The incoming bit stream has a bit rate slightly less than
F (0). Now we will have an
underflow condition. The buffer has been emptied and for a moment in time there are
no further bits to be streamed out. This must be compensated for by the insertion of idle
bits, false bits, or frame. However, it is more common just to repeat the previous frame.
This is also a slip. We may remember the discussion of stuffing in Section 6.8.1 in the
description higher-order multiplexers. Stuffing allows some variance of incoming bit rates
without causing slips.
When a slip occurs at a switch port buffer, it can be controlled to occur at frame
boundaries. This is much more desirable than to have an uncontrolled slip that can occur
anywhere. Slips occur for two basic reasons:
1. Lack of frequency synchronization among clocks at various network nodes
2. Phase wander and jitter on the digital bit streams
Thus, even if all the network nodes are operating in the synchronous mode and synchro-
nized to the network master clock, slips can still occur due to transmission impairments.
An example of environmental effects that can produce phase wander of bit streams is the