ASYNCHRONOUS TRANSFER MODE
There are 12 cells in a PLCP frame. Each cell is preceded by a 2-octet framing
pattern (A1, A2) to enable the receiver to synchronize to cells. After the framing pattern
there is an indicator consisting of one of 12 fixed bit patterns used to identify the cell
location within the frame (POI). This is followed by an octet of overhead information
used for path management. The entire frame is then padded with either 13 or 14 nibbles
(1 nibble = 4 bits) of trailer to bring the transmission rate up to the exact DS3 bit rate.
The DS3 frame, as we are aware, has a 125-
DS3 has to contend with network slips (added/dropped frames to accommodate syn-
chronization alignment). Thus PLCP is padded with a variable number of stuff (justifi-
cation) bits to accommodate possible timing slips. The C1 overhead octet indicates the
length of padding. The BIP (bit-interleaved parity) checks the payload and overhead func-
tions for errors and performance degradation. This performance information is transmitted
in the overhead.
One approach to mapping ATM cells into a DS1 frame is to use a similar procedure as
used with the DS3 PLCP. In this case only 10 cells are bundled into a frame, and two of
the Z overhead octets are removed. The padding of the frame is set at 6 octets. The entire
frame takes 3 ms to transmit and spans many DS1 ESF (extended superframe) frames.
This mapping is illustrated in Figure 20.17. The L2 PDU is terminology used with SMDS.
It is the upper-level frame from which ATM cells derive through its segmentation.
One must also consider the arithmetic of the situation. Each DS1 timeslot is 8 bits long
or 1 octet in length. By definition, there are 24 octets in a DS1 frame. This, of course,
leads to a second method of transporting ATM cells in DS1, by directly mapping ATM
cells in DS1, octet-for-octet (timeslot). This is done by groups of 53 octets (1 cell) and
would, by necessity, cross DS1 frame boundaries to transport a complete cell.
E1 PCM has a 2.048-Mbps transmission rate. An E1 frame has 256 bits representing 32
channels or time slots, 30 of which carry traffic. Time slots (TS) 0 and 16 are reserved.
DS1 mapping with PLCP. (Courtesy of Hewlett-Packard.)
534 ASYNCHRONOUS TRANSFER MODE There are 12 cells in a PLCP frame. After the framing pattern there is an indicator consisting of one of 12 fixed bit patterns used to identify the cell location within the frame (POI). 20.12.2 DS1 Mapping One approach to mapping ATM cells into a DS1 frame is to use a similar procedure as used with the DS3 PLCP.